1. Field of the Invention
This invention relates to amplifiers and more specifically to an improved amplifier output stage.
2. Description of the Prior Art
FIG. 1(a) shows a prior art double buffered (two emitter follower) output stage for an amplifier such as an operational amplifier. The input node (terminal) receives a signal from the input stage of the amplifier (not shown). The first buffer stage includes transistors Q1 and Q3 which drive the second buffer stage transistors Q2 and Q4. Transistors Q5 and Q6 are short circuit protection. Constant current sources I1 and I2 set the quiescent current of this output stage. The voltage supplies are the positive supply voltage V.sub.cc and a negative supply voltage V.sub.ee.
The collector terminals of transistors Q1 and Q3 are respectively connected to voltage references V.sub.ee and V.sub.cc. Other elements of this output stage, including the feedback portion, are conventional but not shown.
This amplifier (in its integrated circuit version) has a disadvantage caused by the parasitic capacitances associated with each of transistors Q1 and Q3 and especially the parasitic capacitance associated with base to collector region capacitance C.sub.jc. There is also the inherent parasitic capacitance of each current source I1 and I2 which adds to the capacitive load at the base terminals of the second buffer stage transistors Q2 and Q4. These capacitances undesirably reduce amplifier performance (response to an input signal) by slowing the switching speed of the transistors, hence undesirably increasing amplifier phase delay and reducing slew rate.
A second prior art amplifier output stage shown in FIG. 1(b) includes three buffer stages. The first buffer stage includes transistors Q1 and Q2; the second buffer stage includes transistors Q3 and Q4; the third buffer stage includes transistors Q5 and Q8. This output stage has the same deficiencies as those described above for that of FIG. 1(a), however, it has more current drive capability.
FIG. 2 shows a third prior art amplifier output stage. As in the previous stages, the signal at node V.sub.IN (equivalent to the input terminal of FIGS. 1(a), 1(b)) is provided from an amplifier input stage (not shown). The amplifier output stage of FIG. 2 has several of the deficiencies described above. First, parasitic capacitance C.sub.jc is present between the base and collector terminals of each of transistors Q3 and Q4 which are the first buffer stage. Similarly, there is a parasitic capacitance C.sub.jc between the base and collector terminals of each of transistors Q5 and Q8 which are the second buffer stage, and a parasitic capacitance C.sub.je between the base and emitter of each of transistors Q5 and Q8. Additionally, there are parasitic capacitances at nodes A and B which are indicated as capacitances C.sub.p.
Also, the capacitor C.sub.c and resistor R.sub.c are connected in series between the input terminal V.sub.IN and the output terminal V.sub.OUT. The purpose of capacitor C.sub.c is to bypass the output stage at higher frequency and improve stability. For a typical amplifier the capacitance C.sub.c is typically a large value, i.e. 10 picofarad or greater. In an integrated circuit this requires an excessive amount of chip surface area (real estate) in a typical MOS process to fabricate such a large value capacitor, thus undesirably increasing the cost of the integrated circuit.
This output stage needs high quiescent current for a large slew rate due to the large parasitic capacitances as described above. This amplifier also exhibits the problem of slow response to high slew (large signal transition) conditions.
There is therefore a need to minimize parasitic capacitance effects in amplifier output stages and reduce the phase delay and improve slew response of the amplifier output stage in order to improve amplifier performance, especially in multi-buffer output stages and during large signal transitions.